1. Field of the Invention
The present invention relates generally to phase locked loops, and in particular to phase locked loops that have switched circuit elements to alter loop bandwidth and related characteristics.
2. Discussion of the Related Art
A phase locked loop (PLL) is a negative feedback system that maintains a constant phase and zero frequency difference between a variable frequency and a reference frequency. Conventional PLL""s include a phase detector element to compare the frequency and phase of an oscillator to that of the reference frequency. The oscillator is then controlled to maintain the constant phase and frequency difference.
The speed with which the phase locked loop can transition from one lock point (or frequency) to the next is a limiting performance factor in many applications. The phase locked loop is therefore often designed with two control system bandwidths (or loop transfer functions): one is a very wide bandwidth that is used to rapidly tune the synthesizer away from the last locked frequency toward the new frequency, and the other is the final narrow bandwidth that is used to provide stable low noise operation during the time that the new frequency is being supplied and the communication channel is active. However, construction of such a dual bandwidth phase locked loop generally requires the use of switches to alter circuit characteristics by selecting different circuit components such as resistors and capacitors. Physically realizable switches and the associated circuits suffer from a phenomenon, known as xe2x80x9ccharge injectionxe2x80x9d, which introduces a disturbance into the other circuit elements at the time the switch is activated. Charge injection generally occurs as the result of the switch control signal entering the signal path via parasitic capacitive coupling. The resulting effect is the injection of an amount of charge equal to the voltage change in the control signal times the size of the parasitic capacitor. The disturbance caused by charge injection may form a new limitation on the speed of the phase locked loop tuning because the disturbance must be resolved by the slower narrow bandwidth PLL control system.
According to one embodiment of this invention a system and method for generating a phase locked loop output frequency signal is provided. The phase locked loop includes a controlled oscillator to generate the output frequency signal in response to a tune signal. A phase detector generates an error signal representing a difference between a reference frequency signal and the output frequency signal. A loop filter having a filter characteristic, filters the error signal and generates the tune signal. The loop filter includes a bandwidth switching circuit to vary the filter characteristic. A charge cancellation circuit is coupled to the loop filter. In response to the error signal, the charge cancellation circuit cancels errors associated with the bandwidth switching circuit.
For a more complete understanding of the invention, its objects and advantages, reference may be had to the following specification and to the accompanying drawings.